PIC18F452-I/L Electronic IC Chip High Performance Enhanced FLASH Microcontroller

PIC18FXX2

28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D

High Performance RISC CPU:

• C compiler optimized architecture/instruction set

  - Source code compatible with the PIC16 and PIC17 instruction sets

• Linear program memory addressing to 32 Kbytes

• Linear data memory addressing to 1.5 Kbytes

• Up to 10 MIPs operation:

  - DC - 40 MHz osc./clock input

  - 4 MHz - 10 MHz osc./clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single Cycle Hardware Multiplier

Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler

• Timer1 module: 16-bit timer/counter

• Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM)

• Timer3 module: 16-bit timer/counter

• Secondary oscillator clock option - Timer1/Timer3

• Two Capture/Compare/PWM (CCP) modules. CCP pins that can be configured as:

  - Capture input: capture is 16-bit, max. resolution 6.25 ns (TCY/16)

  - Compare is 16-bit, max. resolution 100 ns (TCY)

  - PWM output: PWM resolution is 1- to 10-bit,

    max. PWM freq. @: 8-bit resolution = 156 kHz

                                   10-bit resolution = 39 kHz

• Master Synchronous Serial Port (MSSP) module, Two modes of operation:

  - 3-wire SPI™ (supports all 4 SPI modes)

  - I²C™ Master and Slave mode

Peripheral Features (Continued):

• Addressable USART module:

  - Supports RS-485 and RS-232

• Parallel Slave Port (PSP) module

Analog Features:

• Compatible 10-bit Analog-to-Digital Converter module (A/D) with:

  - Fast sampling rate

  - Conversion available during SLEEP

  - Linearity ≤ 1 LSb

• Programmable Low Voltage Detection (PLVD)

  - Supports interrupt on-Low Voltage Detection

• Programmable Brown-out Reset (BOR)

Special Microcontroller Features:

• 100,000 erase/write cycle Enhanced FLASH program memory typical

• 1,000,000 erase/write cycle Data EEPROM memory

• FLASH/Data EEPROM Retention: > 40 years

• Self-reprogrammable under software control

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own On-Chip RC Oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options including:

  - 4X Phase Lock Loop (of primary oscillator)

  - Secondary Oscillator (32 kHz) clock input

• Single supply 5V In-Circuit Serial Programming™ (ICSP™) via two pins

• In-Circuit Debug (ICD) via two pins

CMOS Technology:

• Low power, high speed FLASH/EEPROM technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

• Low power consumption:

  - < 1.6 mA typical @ 5V, 4 MHz

  - 25 µA typical @ 3V, 32 kHz

  - < 0.2 µA typical standby current

Pin Diagrams

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................-55°C to +125°C

Storage temperature ............................................................................................. -65°C to +150°C

Voltage on any pin with respect to V_SS (except V_DD, MCLR, and RA4) ......... -0.3V to (VDD + 0.3V)

Voltage on V_DD with respect to V_SS .......................................................................... -0.3V to +7.5V

Voltage on MCLR with respect to V_SS (Note 2) .......................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss................................................................................ 0V to +8.5V

Total power dissipation (Note 1) ...............................................................................................1.0W

Maximum current out of V_SS pin ...........................................................................................300 mA

Maximum current into V_DD pin ..............................................................................................250 mA

Input clamp current, I_IK (V_I < 0 or V_I > V_DD).......................................................................... ±20 mA

Output clamp current, I_OK (V_O < 0 or V_O > V_DD) .................................................................. ±20 mA

Maximum output current sunk by any I/O pin............................................................................25 mA

Maximum output current sourced by any I/O pin ......................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)........................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)...................200 mA

Maximum current sunk by PORTC and PORTD (Note 3) (combined).......................................200 mA

Maximum current sourced by PORTC and PORTD (Note 3) (combined)..................................200 mA

Note

1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS.

3: PORTD and PORTE not available on the PIC18F2X2 devices.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

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