MT29F32G08CBACAWP-ITZ:C Electronic IC Chips NAND Flash Memory
electronic integrated circuit
,linear integrated circuits
32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features
NAND Flash Memory
MT29F32G08CBACA, MT29F64G08CEACA, MT29F64G08CFACA, MT29F128G08CXACA, MT29F64G08CECCB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 256 pages (1024K + 56K bytes)
– Plane size: 2 planes x 2048 blocks per plane
– Device size: 32Gb: 4096 blocks; 64Gb: 8192 blocks; 128Gb: 16,384 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 5
– Clock rate: 10ns (DDR)
– Read/write throughput per pin: 200 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– tRC/tWC: 20ns (MIN)
• Array performance
– Read page: 50µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 1.7–1.95V, 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when shipped from factory.
For minimum required ECC, see Error Management (page 101).
• RESET (FFh) required as first command after poweron
• Operation status byte provides software method for detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous interface
• Copyback operations supported within the plane from which data is read
• Quality and reliability
– Data retention: 10 years
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 52-pad LGA
– 48-pin TSOP
– 100-ball BGA
Note: 1. The ONFI 2.2 specification is available at www.onfi.org.
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization.
Absolute Maximum Ratings by Device
| Parameter | Symbol | Min1 | Max1 | Unit |
|---|---|---|---|---|
| Voltage input | VIN | -0.6 | 4.6 | V |
| VCC supply voltage | VCC | -0.6 | 4.6 | V |
| VCCQ supply voltage | VCCQ | -0.6 | 4.6 | V |
| Storage temperature | TSTG | -65 | 150 | °C |
Note: 1. Voltage on any pin relative to VSS.
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