NE556DR Integrated Circuit Chip timer ic chip DUAL PRECISION TIMERS
electronics ic chip
,integrated circuit ic
NA556, NE556, SA556, SE556
DUAL PRECISION TIMERS
FEATURES
• Two Precision Timing Circuits Per Package
• Astable or Monostable Operation
• TTL-Compatible Output Can Sink or Source up to 150 mA
• Active Pullup or Pulldown
• Designed to Be Interchangeable With Signetics NE556, SA556, and SE556
APPLICATIONS
• Precision Timers From Microseconds to Hours
• Pulse-Shaping Circuits
• Missing-Pulse Detectors
• Tone-Burst Generators
• Pulse-Width Modulators
• Pulse-Position Modulators
• Sequential Timers
• Pulse Generators
• Frequency Dividers
• Application Timers
• Industrial Controls
• Touch-Tone Encoders
DESCRIPTION/ORDERING INFORMATION
These devices provide two independent timing circuits of the NA555, NE555, SA555, or SE555 type in each package. These circuits can be operated in the astable or the monostable mode with external resistor-capacitor (RC) timing control. The basic timing provided by the RC time constant can be controlled actively by modulating the bias of the control-voltage input.
The threshold (THRES) and trigger (TRIG) levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by using the control voltage (CONT) terminal. When the trigger input falls below trigger level, the flip-flop is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset, and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low. When the output is low, a low-impedance path is provided between the discharge (DISCH) terminal and ground (GND).
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
| SYMBOL | PARAMETER | CONDITION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| VCC | Supply voltage(2) | - | 18 | V | |
| VI | Input voltage | CONT, RESET, THRES, and TRIG | - | VCC | V |
| IO | Output current | - | ±225 | mA | |
| θJA | Package thermal impedance(3)(4) | D package | - | 86 | °C/W |
| N package | - | 80 | |||
| NS package | - | 76 | |||
| θJC | Package thermal impedance(5)(6) | J package | - | 15.05 | °C/W |
| TJ | Operating virtual junction temperature | - | 150 | °C | |
| Lead temperature 1,6 mm (1/16 in) from case for 60 s | J package | - | 300 | °C | |
| Lead temperature 1,6 mm (1/16 in) from case for 10 s | D, N, or NS package | - | 260 | °C | |
| Tstg | Storage temperature range | -65 | 150 | °C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) – TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
(6) The package thermal impedance is calculated in accordance with MIL-STD-883.
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